The present invention relates to a semiconductor memory device and manufacturing method thereof and, more particularly, to a high density semiconductor memory device and manufacturing method thereof having an improved storage electrode structure capacitor that increases the cell capacitance of a memory cell having a stack-type capacitor structure.
Depending upon the reduction of memory cell size, cell capacitance diminution may become a serious obstacle in the integration of DRAM (Dynamic Random Access Memory) chips. Increasing cell capacitance diminution deteriorates the read-out ability of a memory cell and increases the so-called soft errors while making low voltage element operations more difficult, which also results in excessive power consumption. Therefore, there is a need to overcome the problem of capacitance diminution in highly integrated semiconductor memory devices.
In 64 megabyte DRAMs that have a memory cell size of approximately 1.5 .mu.m.sup.2, if a standard two-dimensional stack-type memory cell is used, obtaining sufficient capacitance remains very difficult even when using a high dielectric constant substance such as Ta.sub.2 O.sub.5. Three-dimensional stack-type capacitors have already been proposed to increase the capacitance of memory cells.
For example, the double stack structure, fin structure, cylindrical electrode structure, spread stack structure and box structure are all three-dimensional storage electrode structures that have been proposed to increase the cell capacitance of memory cells.
A three-dimensional stack-type cell capacitor structure, in which the cylindrical structure utilizes the outer surface and the inside surface of a hollow cylinder as an effective capacitive region, may be particularly adopted as a structure suitable for memory cells of the 64 megabyte generation and higher. Ring-structured stack-type capacitors, of the type common to a person skilled in the art, are currently proposed for such high capacity memory structures. The ring structure capacitors improve upon the rather simple cylindrical structure by adding a column inside the hollowed cylinder so that the effective capacitive area becomes the outer surface of the additional inner column as well as the inner and outer surfaces of the outer cylinder (refer to "A Stacked Capacitor Cell With Ring Structure", 1990, 22nd conference on SSDM, part II, pp. 833 to 836).
To better understand the known prior art in the memory structure field, cross-sectional views are shown in FIG. 1A through FIG. 1G, of the process sequence for forming cylindrical storage electrodes having an inner column electrode therein.
In FIGS. 1A and 1B, after sequentially piling an insulating layer 19 and a nitrification layer 22 on a semiconductor substrate 10 which has two transistors both having a source 14, gate electrode 18, and sharing a common drain 16 and a buried bit line 20 formed on the drain regions of the transistor, contact holes 24 are formed by selectively etching both the insulating layer and the nitrification layer deposited on the source region. Thereafter, a first multi-crystalline silicon layer 26 (see FIG. 1C) is deposited to a predetermined thickness on the nitrification layer 22, filling the contact holes 24. An oxide layer pattern 28 is formed by patterning an oxide layer deposited on the silicon layer 26 so that a column can be formed inside of a cylinder. Continuing into FIG. 1D, after forming a column electrode 26a (not shown) by etching back the first polycrystalline silicon layer 26 to a predetermined depth using the oxide layer pattern 28 as a mask, an insulating layer 30a (not shown) having a different etching selection rate from that of the oxide layer pattern 28 is then deposited on the first multi-crystalline silicon layer. While most of insulating layer 30a is thereafter removed by anisotropic etching, a portion of insulating layer 30a is not removed at this time, forming a first spacer 30 on each sidewall of the oxide layer pattern 28 and column electrode 26a. Referring to FIG. 1E, after depositing a second polycrystalline silicon layer 32a (not shown) over the whole surface of the semiconductor substrate, on which the oxide layer pattern 28, the spacer 30 and the column electrode 26a are formed, a cylindrical electrode 32 is completed by forming a second spacer composed of the second polycrystalline silicon onto the sidewall of the first spacer 30, by performing anisotropic etching on both the first and second polycrystalline silicon layers. Thereafter, both the oxide layer pattern 28 and the spacer 30 are removed by wet etching (see FIG. 1F). Storage electrodes S1 and S2 having a column electrode 26b (shown in FIG. 1E) and a cylindrical electrode 32 are now complete. Finally, the formation of the ring-structured stack-type capacitor is completed by coating a dielectric layer 34 onto the whole surface of storage electrode and depositing a third polycrystalline 36 onto the entire resultant surface (see FIG. 1G).
Conventional high-density semiconductor memory devices which utilize the above-described column electrode inside a cylindrical electrode to increase a cell's capacitance by taking advantage of outer column electrode surfaces and inner and outer surfaces of the cylindrical electrode as an effective capacitor area, are being adopted as powerful models in the realization of 64 megabyte DRAMs.
However, the above memory device formed of both cylindrical electrodes and column electrodes which are composed of electrical conductors of different layers, is inconvenient because additional process steps are required due to the different layer compositions. Furthermore, the above cylindrical electrodes are built of duplex spacers on the sidewall of the spacer 30 by anisotropically etching the second polycrystalline silicon layer. In doing so, however, it is uncertain whether the etching of the polycrystalline silicon extends equally over the entire wafer. Because the height of the cylindrical electrode 32 of the central region and that of the edge of the wafer do not coincide, cell capacitance, even on the same wafer, may vary. Additionally, when the object matter to be etched is a polycrystalline silicon, the storage electrodes in the wafer's central region are etched at a different rate than those at the edges, decreasing the memory cell capacitance. As an example of this, FIG. 1G shows a cross-sectional view of an overreached cylindrical electrode which exhibits a memory cell with less-than-expected cell capacitance.
Furthermore, the cylindrical electrode 32 is created by adding another spacer onto the sidewall of the spacer 30 when the top of the cylindrical electrode is anisotropically etched, resulting in the inner edge becoming pointed, and causing the portion of the dielectric layer on top to easily break down. Accordingly, the yield, reliability, and electrical properties of the elements of the memory cell capacitor are undesirable using the previously known techniques of semiconductor manufacturing.
The object of present invention is to provide a high density semiconductor memory device having a storage electrode structure which sufficiently satisfies the cell capacitance requirement for a 64 megabyte DRAM, and higher capacity DRAMs by solving the various problems involved in the above described conventional technology as known heretofore.